Field effect transistors (FETs) differ in channel geometry and in their functional parameters (e.g., carrier mobility). In the transistor on-state, a conductive inversion layer (channel) is formed between two source/drain regions of the FET. In planar FETs, the channel is oriented to one single plane, whereas in 3D-channel FETs the channel is oriented to at least two different planes. In an integrated circuit, FETs of different structure and/or with different characteristics may be combined on one single chip.
Conventionally, hybrid substrates with different crystal orientations have been used to fabricate a high performance CMOS (complementary metal oxide semiconductor) structure comprising an n-channel FET (n-FET) and a p-channel FET (p-FET) with matched parameters on one single chip. Manufacturing of hybrid substrates includes complex and time-consuming processes (e.g., direct wafer bonding, etching, and epitaxy).